In high-power field effect transistors, in order to increase the power output, in the past field plates have been provided. These field plates help reduce the peak electric field and also help control some of the surface charge so that the device is able to operate at higher voltages and thus operate at higher power outputs. It is noted that these FET-based amplifiers are designed to operate in the MegaHertz range up to the tens of GigaHertz.
By way of background, silicon-based field effect transistors and more recently gallium arsenide-based field effect transistors have, been used to provide the architecture for high-power devices.
While silicon and gallium arsenide devices have been utilized in the past, more recently these high-power devices take advantage of the properties of gallium nitride material to increase the voltage that can be applied to the device to in excess of 40 volts, thus to increase output power. It is of course noted that the power for the transistor amplifier depends on the size of the device. Assuming a power density that is normalized to the device periphery, it would be desirable to obtain about 10 watts per millimeter biased on the 40-volt range. This 10-watt-per-millimeter design goal is about ten times what one can achieve using silicon or gallium arsenide.
In typical applications for field effect transistor amplifiers such devices operate up to about 100 watts output power, although several hundred watts in output power are not out of the question for discrete devices.
The reason that the industry has gravitated to gallium nitride as opposed to gallium arsenide is the fact that gallium nitride is a wide band-gap semiconductor material with a relatively high saturated electron velocity of 1.5-2×107 cm/s. A wide band-gap material is a material having a property that allows high electric fields to be applied without the material breaking down. As a result, one can apply higher voltages to devices, with higher voltages leading to higher RF output power for the individual devices.
However, due to the lack of reproducible lattice-matched substrates and relative immaturity of AlGaN/GaN processing technology, many bulk and surface defects exist in the device material. Bulk traps, due primarily to threading dislocations in the material, reduce the sheet carrier concentration, and therefore microwave performance of the device. Bulk and surface traps give rise to gate and drain lag that is a source of dispersion in the device, which impacts large-signal power performance.
Advanced device designs have been pursued in the industry to reduce trapping effects and boost GaN device performance and reliability. Among these designs, implementing a field plate on a dielectric layer at the drain side of the gate electrode has resulted in the most significant enhancement. The function of a field plate is to modify the electric field profile and to decrease its peak value at the gate edge, hence reducing trapping and increasing breakdown voltage. Power densities exceeding 30 W/mm at 4 GHz has been demonstrated with a field plate design.
There are basically two ways of fabricating field plate electrodes, one being a dry etch process, which creates an integrated gate/field plate structure. The other method utilizes field plates that are separately defined and are externally connected to the gate or source electrode on the chip.
S. Karmalkar and U. K. Mishra, “Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using a Field Plate,” IEEE Trans. Electron Devices, vol. 48, pp. 1315-1521, 2001 discloses a prior art method in which the field plate is defined as part of the gate electrode.
Y.-F. Wu, A. Saxler, M. Moore, R. P. Smith, S. Sheppard, P. M. Chavarkar, T. Wisleder, U. K. Mishra, and P. Parikh, “30-W/mm GaN HEMTs by Field Plate Optimization,” IEEE Electron Device Lett., vol. 25, March 2004, and Y.-F. Wu, M. Moore, T. Wisleder, P. M. Chavarkar, U. K. Mishra and P. Parikh, “High-gain microwave GaN HEMTs with source-terminated field-plates,” IEEE IEDM Technical Digest, pp. 1078-1079, December 2004, disclose a method in which the field plate is separately defined but directly connected to the gate or source electrode on chip.
One criterion for the provision of a field plate electrode is that one has to place the field plate electrode very close to the gate of the field effect transistor for it to be effective. In the Karmalkar et al. method, one derives an integrated structure such that the field plate and the gate are in essence one electrode. Thus there is no spacing problem.
This technique is generally referred to as a dielectric-assisted T-gate process. In this process one puts a passivation layer on a substrate before any gate metal is put down. One then utilizes some etching technique, usually dry chemistry or plasma etching, to open a trench in the passivation layer to contact the semiconductor substrate. After this process of opening up the contact area, one deposits metal that fills the trench and also forms the field plate extension that goes to either side of the actual gate connection.
Note that the field plate allows a spreading of the electric field so that the total voltage that can be applied to the device is higher. The field plate extension is also useful in controlling the surface states that are close to the gate, which helps with reducing any dispersive effect that comes from the surface states in semiconductors.
However, the dry etch technique described above is relatively difficult to control because when one has a plasma etch with active ions that are hitting the surface to perform the removal of the passivation layer, one always has to do an over-etch to ensure complete removal of passivation dielectric material. During the over-etch, the semiconductor material at the bottom of the trench is exposed to the plasma and because of the energy that the ions carry, the semiconductor substrate is damaged. In particular, there is atomic-level damage in the semiconductor itself that can penetrate up to hundreds of angstroms. Depending on the plasma energy, as much as 200 to 300 angstroms of damage can result, which is quite normal in the dielectric-assisted T-gate process.
Damage to the gate area causes a reduction in the power output of the device because many electronic traps are generated. The traps are material defects in the crystal that can hold electrons. One does not want to retain electrons in the gate area because one wants the electrons to be in the active channel where the current is being carried. If the traps hold some of the electrons, the result is that one does not have as many electrons as one would like to carry the current. The result is that the power output of the discrete device is significantly reduced.
There is another problem with respect to the etching technique described above and that is one of reliability. When one has material defects, the material itself is less capable of holding the high electric field that is applied to the physical areas of the device. Thus, the material utilized in the field effect transistor degrades over time if dry etching is used, which means that the reliability of the device is lower than one would expect, assuming no plasma damage.
Moreover, with the dielectric-assisted T-gate approach, the critical gate dimension formed by dry etching and opening is considerably less well controlled than is desired. It is this gate dimension that is critical to device operation.
The above-mentioned over-etching results in trench sidewalls whose positions are not sufficiently well defined. When the gate metal is deposited in the trench, it spreads out in the over-etched areas. This means that the size and shape of the gate contact area with the substrate cannot be well controlled.
In order to eliminate the problems associated with the dielectric-assisted T-gate approach for forming a field plate at the gate of the device, a separate gate/field plate approach has been used in which the gate and the field plate are deposited in separate lithography steps and separate metallization steps. This gets away from the dry etch damage as well as the difficulty in dimension control as mentioned above.
Separating the field plate and the gate works to some extent but one cannot put the field plate exactly next to the gate contact of the semiconductor. At the very least, the field plate has to be separated by the thickness of the passivation layer. It will be appreciated that the extra separation makes the device performance inferior to the integrated approach above.
In short, the field plate is separated by as much as the thickness of the passivation layer. The passivation layer is typically on the order of 1,000 angstroms for normal devices. Thus there is quite a substantial distance from the edge of the gate electrode to the field plate. If the gate dimension is on the order of 0.25 microns and assuming a 1,000-angstrom passivation layer, this is equivalent to a spacing of 0.1 micron out of the 0.25-micron dimension, which is substantial. There is thus quite a substantial distance from the edge of the gate electrode to the field plate.
Also, when utilizing a separate gate and field plate, one has to connect them externally together. When one has an electrical contact that is external to the active area of the device, the field plate and the gate plate connect to the same bar of metal outside so they are under the same electrical bias. This presents a number of problems.
First, this technique opens up the device to potential metal connect reliability issues because one has a separate metal connect that one is making. Moreover, this technique also induces another effect when one is operating at high frequencies. There is a phase difference between the electrical signal traveling down the field plate and the one going down the gate. If one is feeding them at the same point, because the gate and the field plate are presenting different impedances to the point that one is applying the RF to, the signals travel slightly out of phase and could potentially lead to a fighting out-of-phase condition between the field plate and the gate. The result is that one is not extracting the maximum effect that one would seek from the utilization of the field plate.
In summary, the prior art methods may have a number of disadvantages. The prior art method of etching all the way to the semiconductor surface results in damage to the surface, leading to increased leakage current and poor reliability and device performance. Damage is particularly severe with “dry” etching techniques such as Reactive Ion Etching or Inductively Coupled Plasma etching. Alternative wet chemical etching techniques are often less damaging, but a wet etch processes result in undesirable “undercut” of the resist pattern, leaving a widened and non-uniform gate length. In the separate gate and field plate technique, the gate is defined with standard lithography techniques, after which the passivation dielectric is deposited. This eliminates the need to etch through the dielectric, but results in a “gap” between the gate and field plate, reducing field plate effect and requiring that the electrical connection be made remotely.
A need, therefore, exists for an improved method for fabrication of field effect transistor gates with or without field plates. More specifically there is a need to: (1) eliminate damage inherent in the dielectric gate etch process, (2) decrease gate leakage current which is the result of damage during formation of the gate, and (3) reduce or eliminate the impact of traps in the gate/drain region of the transistor.